In dynamic random-access memory (DRAM) device/flash memory fabrication, implanting a semiconductor dopant species into the polycrystalline silicon (polysilicon) gate electrodes beneficially increases conductivity. The gate electrodes may be formed by depositing amorphous silicon on a thin gate oxide layer and then annealing the wafer to transform the deposited silicon from the amorphous state to a polycrystalline state. The polycrystalline silicon gate layer thus formed may be approximately 50 nm to 80 nm thick. The implanted species is one promoting p-type conductivity in silicon, such as boron, or n-type conductivity, such as arsenic, phosphorous or antimony. The gate electrode can also be made by certain metals such as TiN or W.
Write/read speed and retention time are key factors of a DRAM. Better performance, such as high drive-current and low off-current of cell transistors, is key to improving the key factors. Thinner gate oxide can effectively improve performance. As such, the layer thickness of the gate oxide continues to be reduced. DRAM scaling has negatively led to increased non-uniformity in gate oxide thickness of cell transistors. In some cases, a bottom gate oxide within an opening or channel can be as much as 3 nm thinner than the gate oxide formed on the sidewalls of the opening or channel. A thinner bottom gate oxide brings significantly reliability risk for cell transistors.